1. Field of the Invention
This invention relates to integrated circuit designs, and more particularly to a power distribution network for wafer scale integrated circuits that is tolerant of short circuits in the distribution network, and a related method for removing such short circuits from the network.
2. Description of the Related Art
An important requirement for the successful fabrication of wafer scale integrated circuits (ICs) is an ability to tolerate manufacturing defects. A considerable amount of investigation has been conducted towards enhancing the defect tolerance of memory circuits and, to a lesser degree, random logic circuits. In general, redundant logic circuits are fabricated on the chip and used as spares in case one of the primary logic circuits is not working properly. If a faulty logic circuit is located, it is removed from the remainder of the IC (generally by using a laser to cut its connection), and a redundant circuit module is switched in to replace it. The use of redundant logic modules is discussed in Moore, "A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield", IEEE Proc., Vol. 74, No. 5, May 1986, pp. 684-698.
Aside from defects in the logic circuits themselves, manufacturing flaws in the power supply busses for these circuits can also significantly degrade the yield rates. A power bus is subject to several kinds of random defects, including open circuits, short circuits between two busses on the same layer, and short circuits between a power bus and either another bus or another part of the circuit structure on a different layer. Short circuits between busses on different layers are the most difficult case from the viewpoint of detection and removal.
An open circuit defect usually manifests itself by disabling the supply of power to a certain portion of the circuitry. This type of defect is not fatal, i.e., it does not render the whole die (or wafer in the case of wafer scale integration) untestable. Open circuits can be tolerated to some extent if all major power busses have considerable width and receive power from both ends. Short circuits, on the other hand, can be fatal depending upon the impedance of the layers involved. If the power bus short circuit involves high impedance layer such as a polysilicon, diffusion or well layer with a resistance on the order of 10 ohms per square or larger, the defect would not be fatal to the metal layered global power busses. However, a circuit module underneath such a short would not function correctly, and would have to be replaced with a substitute circuit module.
It is the short circuits involving the medium impedance layers (resistance on the order of 1 ohm per square) or low impedance layers (such as metal, with resistance on the order of 0.1 ohms per square) that have the potential to be fatal and must be identified and removed. While inter-layer short circuits between a power-carrying metal layer and the substrate can be fatal, the incidence of such faults is quite low. The frequency of short circuits along a crossover of two metal power lines (separated by a dielectric layer) is considerably higher.
The general approach to overcoming faults on power supply lines has been to break up the power distribution network and the associated circuits into many different segments, and to connect up only the good segments after testing them. Power transistors as the connecting mechanism are discussed in Fried, "An Analysis of Power and Clock Distribution for WSI Systems", Proc. Workshop on Wafer Scale Integration, 1986, pp. 127-142, while the use of programmable or laser links is discussed in Raffel, "On the Use of Non-Volatile Programmable Links for Restructurable VLSI", Proc. Caltech Conf. on VLSI, 1979, pp. 95-104, and Chapman, "Laser Linking Technology for RVLSI", Proc. Workshop on Wafer Scale Integration, 1985, pp. 204-215. An additional layer of metal may also be used as the connecting mechanism.
The above approach is inherently inefficient. If the number of segments is not very large, a single defect can still render significant portions of the circuits inoperative. If the number of segments is increased, the wafer area required for the test input/output interface drivers and pads increases, and the time required for activating laser links also increase proportionately.
In attempting to optimize the circuit design, rather than to accommodate unintended short circuits, a number of imaging techniques have been used in the IC industry for failure and yield analysis. In one such technique, the circuit to be analyzed is coated with a film of cholesteric liquid crystals, and the substrate is heated to slightly below the liquid crystal's transition temperature. Current is then applied to the circuit so that hot spots in the circuit are above the transition temperature, causing the liquid crystal above the hot spots to turn black. This technique is disclosed in Hiatt, "A Method of Detecting Hot Spots on Semiconductors Using Liquid Crystals", Proc. Reliability Physics Symposium. 19, 1981, pp. 130-133. Infrared thermal imaging has also been used to detect hot spots for circuit analysis purposes, as discussed in Leftwich and Kintigh, "The Infrared Microimager and Integrated Circuits", SPIE, Vol. 104, Multidisciplinary Microscopy, 1977, pp. 104-110.
Infrared imaging is generally preferable to liquid crystal detection because it is more efficient, and is also free of the possible device damage and contamination by the chemicals associated with liquid crystal processing. Infrared thermal imaging uses radiation with wavelengths of about 2 to 15 microns. When external power is applied to the circuit, hot spots due to short circuits in the power distribution network usually radiate energy with a wavelength within this range. However, in some cases this technique does not accurately resolve the location of the hot spot. Spatial resolution is limited not only by the long radiation wavelength, but also by the nature of the short circuit and the heat conduction characteristics of the materials surrounding the short. A relatively large area may be heated around the actual short circuit location, and the hot spot may be so blurred that it cannot be detected at all. Also, for small area or partial short circuits in which the short circuit current density is relatively low, there may not be enough heating to produce a detectable hot spot in the first place.